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Beitragsrückblick für SiSoftware Sandra 2021 (die neuesten Beiträge zuerst)
ocinside Erstellt: 9:45 am 19. Okt. 2022
SiSoftware Sandra 2021 31.109 wurde online gestellt und kann nun von unserem Server heruntergeladen werden :thumb:


- Benchmarks, Hardware Support updates and fixes
Cluster Bandwidth Contribution: All Cache/Memory Benchmarks
It is the sum of the bandwidth of all cores in each cluster (%)
Reveals how much the big/P & LITTLE/E core clusters have contributed compute power wise to each benchmark score in percent: e.g. on Intel 12600K - Memory Bandwidth Benchmark:
60% big/P Cluster - 40% LITTLE/E Atom cluster
Core Bandwidth Ratio: All Cache/Memory Benchmarks
It is the ratio of the big/P Core vs. LITTLE/E core bandwidth (ratio)
Reveals just how much more performant the big/P Cores are vs. the LITTLE/E cores.
2.15x big/P Core - 1.x LITTLE/E Atom core

- Additional Hardware Support
Additional AMD Ryzen 7000 (Zen4) support
Enabled DDR5 SPD (Hub, PMIC, TS) AMD information
Additional Intel Sapphire Rapids (SRP-X/EX) support
Enabled DDR5 SPD (Hub, PMIC, TS) Intel information

- Example of performance contribution/ratio on Intel Core i5 12600K (ADL):
Cluster Bandwidth Contribution (per Cluster type)
Integer Memory Bandwidth : 64% big Cores Cluster – 32% LITTLE cores Cluster
Float Memory Bandwidth : 65% big Cores Cluster – 32% LITTLE cores Cluster
L1D (1st Level) Data Cache Bandwidth : 78% big Cores Cluster – 18% LITTLE cores Cluster
L2 (2nd Level) Unified/Data Cache Bandwidth : 89% big Cores Cluster – 7% LITTLE cores Cluster
L3 (3rd Level) Unified/Data Cache Bandwidth : 90% big Cores Cluster – 7% LITTLE cores Cluster
Note: Here we sum the memory bandwidth performance contribution for all cores in the type of cluster.
Note2: This feature also works on Arm64 big.LITTLE / DynamicQ SoCs, it is not tied to x86 Intel hybrid systems.
Cluster Bandwidth Ratio (per core type)
Integer Memory Bandwidth : 1.3x big-Core – 1.0x LITTLE-core
Float Memory Bandwidth : 1.4x big-Core – 1.0x LITTLE-core
L1D (1st Level) Data Cache Bandwidth : 2.9x big-Core – 1.0x LITTLE-core
L2 (2nd Level) Unified/Data Cache Bandwidth : 8.5x big-Core – 1.0x LITTLE-core
L3 (3rd Level) Unified/Data Cache Bandwidth : 8.6x big-Core – 1.0x LITTLE-core
Note: Here we divide the cluster performance contribution by the number of cores in each cluster – and then work out the big/LITTLE ratio. If SMT is enabled or not, we still only count the number of cores per cluster, not threads.

ocinside Erstellt: 7:30 am 7. Sep. 2022
SiSoftware Sandra 2021 31.104 wurde online gestellt und kann nun von unserem Server heruntergeladen werden :thumb:


- Benchmarks, Hardware Support updates and fixes
Parallelism: All CPU/Memory Benchmarks
Additional Multi-Threaded big/P Cores Only aka only using threads running on big/P cores (SMT)
Note that as (current) LITTLE/E Atom cores do not support SMT, there is no corresponding option for them yet

Cache & Memory Bandwidth Benchmark
Improved/fixed hybrid bandwidth workload allocation when all cores types are used; e.g. on Intel 12600K:
Memory Bandwidth Improvement: 49GB/s to 56GB/s: +14% improvement (float AVX2/buffered)
L1D Cache Bandwidth – not affected/improvement
L2 Caches Bandwidth fix: 145GB/s to 836GB/s
L3 Cache Bandwidth fix: 56GB/s to 452GB/s

Cluster Performance Contribution: All CPU/Memory Benchmarks
It is the sum of the performance of all cores in each cluster (%)
Reveals how much the big/P & LITTLE/E core clusters have contributed compute power wise to each benchmark score in percent: e.g. on Intel 12600K - CPU Arithmetic Benchmark:
80% big/P Cluster - 20% LITTLE/E Atom cluster

Core Performance Ratio: All CPU/Memory Benchmarks
It is the ratio of the big/P Core vs. LITTLE/E core performance (ratio)
Reveals just how much more performant the big/P Cores are vs. the LITTLE/E cores.
2.15x big/P Core - 1.x LITTLE/E Atom core

- Future Hardware Support
Additional AMD Ryzen 7000 (Zen4) support
Enabled DDR5 SPD (Hub, PMIC, TS) AMD information
Additional Intel Sapphire Rapids (SRP-X/EX) support
Enabled DDR5 SPD (Hub, PMIC, TS) Intel information


ocinside Erstellt: 9:13 am 24. Juli 2022
SiSoftware Sandra 2021 31.98 R15 wurde online gestellt und kann nun von unserem Server heruntergeladen werden :thumb:


CUDA GP-GPU Benchmarks
- Updated to CUDA SDK 11.8 with nVidia Ada support GeForce RTX 4090, et.]

Memory Bandwidth Benchmark
- 3-5% bandwidth increase due to L1D block/prefetch optimisations e.g. AVX512 AMD Zen4, Intel ICL-SP, future arch.

Memory Latency Benchmark
- "In-Page Random" memory access latency pattern – additional TLB ranges randomisation in addition to the randomisation within each TLB range. Credit Rob Williams @ TechGage – many thanks!
Benchmark now fails (does not run at all) if TLB information cannot be detected, e.g. CPU does not report it.
This change affects both Data and Code latencies.

- Note that the other tests "Full Random" and "Sequential" memory access patterns – are *not* affected – as the pattern is not affected by TLB data.

- It is always recommended to use "2MB/large" pages rather than "4kB/normal" pages in order to minimise "TLB miss" penalties which is the reason for the “in-page random” test. Please see How to enable large/huge memory pages in Windows.

Cryptography Benchmark
- 3-5% bandwidth increase due to L1D block/prefetch optimisations e.g. AVX512-VAES AMD Zen4, Intel ICL-SP, future arch.

Client (GUI)
- Light/Dark-mode colour optimisations

ocinside Erstellt: 6:44 am 5. Juli 2022
SiSoftware Sandra 2021 31.97 R14c wurde online gestellt und kann nun von unserem Server heruntergeladen werden :thumb:


Memory Latency Benchmark
- "In-Page Random" memory access latency pattern – TLB range fix – that resulted in too-low memory score (latency) to be reported on modern Intel systems (e.g. AlderLake with large L3 cache).
- Better random number generator (2^32 vs. 2^15 states) in order to defeat any possible access pattern detection by the CPU.
- Note that the other tests "Full Random" and "Sequential" memory access patterns – arenot- affected - as the pattern is not affected by TLB data.
- It is always recommended to use "2MB/large" pages rather than "4kB/normal" pages in order to minimise TLB miss penalties which is the reason for the "in-page random" test.
- Reverted to testing latencies of all cores thus "Multi-Core" rather than just 1 thread/core "Single-Core" so that on hybrid systems (AlderLake, RaptorLake, etc.) the average/overall latency does not favour just to Big/P cores. This does increase run-time of test proportional with number of cores.

Memory Bandwidth Benchmark
- Increased buffer sizes for modern processors to match L1D cache size

Cryptography Benchmark
- fixed HWA code paths (AES, SHA) not engaging R13x regression

Hardware
- Resolved L2, L3, L4 caches counts detection R13x regression


ocinside Erstellt: 14:06 am 14. Juni 2022
SiSoftware Sandra 2021 31.93 R14 wurde online gestellt und kann nun von unserem Server heruntergeladen werden :thumb:


- Hardware
Resolved L2 & L3 cache count detection [R13x regression]
- Client (GUI)
Light/Dark-mode font optimisations

Weniger Antworten Mehr Antworten
ocinside Erstellt: 7:32 am 19. Mai 2022
SiSoftware Sandra 2021 31.88 R13 wurde online gestellt und kann nun von unserem Server heruntergeladen werden :thumb:


- Hardware
Intel 4th gen Intel Xeon Sapphire Rapids ADL-SP AVX512+ support
Intel 3rd gen Intel Xeon Whitley Ice Lake ICL-SP AVX512+ support
AMD Ryzen 6000 Mobile platform
Future hardware support

- Benchmarks
Memory Bandwidth Benchmark: fixed failure with multiple cores/threads CPUs e.g. ICL-SP
Cache Bandwidth Benchmark: fixed failure with multiple cores/threads CPUs e.g. ICL-SP

- Client GUI
Light/Dark-mode font optimisations
Icon dynamic colour customisation

ocinside Erstellt: 16:13 am 29. März 2022
SiSoftware Sandra 2021 31.81 R11 wurde gerade online gestellt :thumb:

Hardware Support, Updates & Fixes
- Intel AlderLake, RaptorLake – memory module sizes
- AMD Ryzen 5000+ series – memory module sizes
- Dark-mode detection
- Light/Dark-mode colours for benchmark items
- Light/Dark-mode font optimisations
- Icon dynamic colour customisation

ocinside Erstellt: 7:14 am 1. März 2022
SiSoftware Sandra 2021 31.78 R10a wurde gerade online gestellt :thumb:
ocinside Erstellt: 7:48 am 23. Feb. 2022
SiSoftware Sandra 2021 31.76 wurde online gestellt und kann nun von unserem Server heruntergeladen werden :thumb:


Multi-Media Benchmarks
- Integer Int16 / Int32 Arm64 128-bit NEON Benchmarks
+41% Int16 16×16 > 32 improvement [Pi4: 51MPix/s vs. 36.7]
+28% Int32 32×32 > 64 improvement [Pi4: 32MPix/s vs. 24.8]
+5% Int64 64×64 > 128 improvement
- Preliminary SVE/SVE2 Benchmarks

Cryptography Benchmarks
- Multi-Buffer Arm64 128-bit NEON Hashing Benchmarks
+100% improvement SHA2-256, SHA1
- Preliminary AES HWA hardware acceleration support AES256, AES128
- Preliminary SHA HWA hardware acceleration support SHA2-256, SHA1

Memory & Cache Benchmarks
- Buffered Arm64 128-bit NEON Integer/Floating-Point Benchmarks
+33% bandwidth improvement [Pi4: 8GB/s vs. 6GB/s]
- Preliminary SVE/SVE2 Benchmarks

Inter-Thread/Core/Module/Node/Package Transfers
- Arm64 128-bit NEON Transfers
+25% bandwidth improvement

Hardware
- AMD EPYC Milan module/core detection issues
- AMD EPYC Milan additional support

ocinside Erstellt: 14:02 am 31. Jan. 2022
SiSoftware Sandra 2021 31.73 wurde online gestellt und kann nun von unserem Server heruntergeladen werden :thumb:


ARM64 AArch64 Support
- ARM Cortex AArch64 CPU/SoCs including A7X, A5X, A700, A500, X1
- Qualcomm Snapdragon 7c, 8cx / Kryo CPU/SoC
- Apple M1 through virtualization, e.g. Parallels VM
- Microsoft SQ1, SQ2 Surface X
- Broadcomm BCM CPU/SoC in Raspberry Pi 4B and the older Pi 3B+, 3B

Hardware
- Intel RaptorLake RPL 13th Gen Core preliminary support S/H
- Resolved memory reporting issues on Intel AlderLake ADL 12th Gen Core, RaptorLake RPL 13th Gen
- ARM NEON support for both AArch64 & AArch32

Memory & Cache Benchmarks
- Dynamic bandwidth workload allocator for big/LITTLE arch e.g. ARM DynamiQ, Intel Hybrid
Buffered Memory Bandwidth
Direct Cache L1D, L2, L3, L4 Bandwidth

CPU Benchmarks
- Dynamic work-allocator enabled by default on all benchmarks except where not possible
- Additional Core/Thread selection support
big/P Cores Only but not threads – thus 8T – only Core cores
LITTLE/E Cores Only thus 8T – only Atom cores
Multi-Threaded big/P Cores – only Core cores w/SMT – thus 16T
Single Thread big/P Core – 1T thus single Core core
Single Thread LITTLE/E Core – 1T thus single Atom core

New Operating System Support
- Windows 11
- Windows Server 2022 LTSC 21H2
- Windows Server vNext Windows 11 kernel

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